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Monday, November 28, 2011

Economic Shift Register interfacing

We came across an interesting technique of interfacing Shift Registers. We all know that the Shift Registers need 3 I/O lines to interface at minimum.
However if we can cleverly time  the Load and Clocking pulses to get the job done:
The above circuit times the PL pulse of the 74HC165 with the Clock pulse. It uses the limit of the CMOS threshold levels in 74HC14.
Even more interesting is that if this could be done over a single I/O line by alternately configuring it as an input or output.
For Detailed info Refer:

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